Modern backplane bus based computer systems typically define an address space that encompasses all of the memory locations provided by all of the components coupled to the backplane bus. The components of the computer system can include a shared main memory. In this manner, each processor of the system can generate addresses for direct access to all of the memory locations available in the system. For example, the Futurebus backplane bus protocol provides for a 32 bit bus address.
However, each processor of the system may include a 64K byte RAM local memory wherein a 16 bit address is sufficient for access to the locations of the local memory. Moreover, each processor may also read and write data blocks to local memory in byte or word sized blocks and utilize 16 line data buses, whereas the bus operates with 32 bit or longword sized data block transfers. Thus, it is often necessary to provide a data transfer device between the processor and a bus interface to accommodate the generation of full bus addresses and to pack data blocks for transfer to the data lines of the bus and to unpack data blocks received from the bus for input to the processor.
In addition, a bus transaction to affect a data transfer over the bus requires an arbitration for the bus and transitions through bus phases pursuant to a protocol to properly transmit address information and data blocks over the bus. Typically, the bus arbitration and protocol functions are performed by the bus interface. However, a processor must ordinarily wait for data to be received from the bus or to transfer data onto the bus before continuing processor operations. Thus, the data transfer device should perform data buffering between the processor and bus to enable a processor to continue operating before a bus transaction is completed.